The present invention relates in general to integrated circuits. More particularly, the present invention relates to memory cells, especially of the dynamic random access (DRAM) type which are compatible with a process for fabricating a device incorporating such a memory and CMOS components.
Conventionally, a DRAM memory is in the form of rows and columns at the intersections of which are memory cells consisting of a memory element, typically a capacitor, and of a switch for controlling this memory element, in general an MOS transistor.
A DRAM-type memory cell (FIG. 1) consists of a control MOS transistor T and a storage capacitor C which are connected in series between an electrical earth M and a bit line BL. The gate of the control transistor T is connected to a word line WL. The transistor T controls the flow of electrical charges between the capacitor C and the bit line BL. The electrical charge on the capacitor C determines the logic level, 1 or 0, of the memory cell. When reading the memory location, the capacitor C discharges into the bit line BL. To read the value of the electrical charge on the storage capacitor C quickly and reliably, the capacitance of this capacitor must be high compared with the capacitance presented by the bit line BL during the reading phase.
A large number of DRAM cells formed in this way are grouped together in the form of a matrix so as to generate a memory plane which may comprise millions of elementary cells. For some applications, the memory plane lies within a complex integrated circuit. One therefore speaks of on-board memory.
The memory elements are structures based on capacitors having a first electrode consisting of a base in contact with a diffusion region of an MOS transistor and of an approximately horizontal plateau. Memory capacitors also have a very thin dielectric and a second electrode common to several capacitors and consisting of a continuous conducting layer, for example made of polycrystalline silicon, lying above the very thin dielectric. The second electrode is then covered with a thick dielectric layer.
It is necessary to produce an electrical contact between a second electrode of a capacitor and the upper surface of the said thick dielectric layer on which a level provided with conducting tracks, also called a metallization level or conducting level, may be placed.
Conventionally, this electrical contact may be made by providing a connection structure formed, for example, during production of the dielectric layer, extending either above the capacitor or offset with respect to the latter.
This technique has a major drawback in so far as, in particular, because of the conformation of the capacitor, the electrical contacts between the connection structure and the electrode of the capacitor are relatively poor in quality.
Moreover, since this connection structure is generally coupled to a via ensuring connection to the substrate, the difference in depth between the capacitor and the latter greatly complicates the production of the circuit, in particular as regards the etching phases. The term “via” is understood to mean, within the context of the present invention, a hole filled with an electrically conductive material capable of forming an electrical connection between two or more levels of an integrated circuit.
Finally, in order to reduce the fabrication costs, the problem of how to simultaneously produce all the electrical contacts arises.